A New Arbitration Circuit for Asynchronous Multiple Bus Multi Processor Systems

In a bus-based mult iprocessor system, a bus arb i t ra t ion c i r c u i t i s necessary to assign the bus(es) to the requesting devices. A number of a rb i te r designs for singlebus mult iprocessor systems a re avai lable in the ex is t ing l i terature. There a re two types o f arb i ters : synchronous and asynchronous. In a synchronous a r b i t e r , the a r b i t r a t i o n process repeats ( i f there i s any request) a f ter a ce r ta in i n te rva l o f t ime. Whereas, in an asynchronous a rb i te r the a rb i t ra t i on process s tar ts as soon as a request for the shared resource(s) i s made b y a device Asynchronous a rb i te rs a re more complex but faster than synchronous arbiters. A l imi ted number of asynchronous a r b i t e r designs for mu l t i p le bus systems a r e repor ted i n the l i t e ra tu re This paper f i r s t discusses some design f laws of an ex is t ing asynchronous a r b i t e r f o r m u l t i p l e bus systems, and then i t shows an improvement of the exist ing arb i te , and f i na l l y i t presents a new asynchronous arb i ter . This new a rb i te r i s v e r y s imple and easy to implement. The a rb i te r was b u i l t and tested. A s imulat ion sof tware has been developed to measure the performance o f the new a r b i t e r . The performance was measured i n terms of fairness and mean-arbitfalion-time.